These questions are tick marked from J. S. Katre (Tech max publication) – 3rdedition

Yellow shaded questions are the most IMP questions for those chapters. Follow the instruction given in red color.

Chapter no.- 6 and 7 can be avoided if you want.

Prepare- 2, 3, 4, 5, 8, 9 passing with average marks

Prepare – 1, 2, 3, 4, 5, 8, 9 chapters for passing with good marks

Prepare all the chapters for attempting all the questions in GTU examination...



download file from here
Wednesday 21 November 2012

exam forms available


To all my PIET friends
attention pls 
exam form avi gaya che
and 2 days ma fill up karvana che
means 23 last date chhe...
fee receipt compulsory che i-card nu pakku khbr nai bt hoy to vadhare saru..
also about the fees last time 125 per subject hata...so avakhte b 750 hoy kadach....n jo atkt hoy koi b subject ma to bija extra ena alag...
bt first sem pase thi 200 per subject collect karela so e rite apda pan collect kare to 1000 rs thay....
so minimum 750rs to max 1500 n fee receipt to laij avavu....
n 9:30 pachhi n 11 pehla...pot pota na class room ma jai receipt collect kari levi...a vakhte admin ma thi form collect nai karva na....department mathi karva na chhe

thnk u

p.s.
utsav sir said that first we have to collect receipt @9:30 from out class rooms n then we have to submit it in admin cell....
afain tellin u fee receipt n icard le k ana koi prob na ho isliye
Monday 5 November 2012

coa chap9th 10th



COA
Ch:9
1.Explain SISD , SIMD , MISD ,MIMD
2.Explain pipelining process with an example and figure.
3. Derive formula to find speed up pipeline & non-pipeline process. show how S=R.
4.Explain arithmetic pipeline with an example &flowchart.
5.Explain 4 segment instruction pipeline with flowchart & timing diagram .

Ch:10
1.  Explain hardware implementation of addition & subtraction algorithm with flowchart.
2.  Explain Booth algorithm with its hardware implementation.
3.  Explain BCD adder with diagram.
4.  Explain divison algorithm with hardware implementation.
5.  Differentiate between attached array processor.